CPU Cache Hierarchy

L1/L2/L3, cache lines, hits vs misses, spatial locality — and why loop order can make identical code run several× slower

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steps

Act 1 of 8·The Speed Gap

step 1

where the data islatency

< 1 cycle

L1 cache

~4 cycles

L2 cache

~12 cycles

L3 cache

~40 cycles

Main RAM

~200 cycles

SSD

~100 µs

HDD seek

~10 ms

the gap between L1 and RAM is ~50×, between RAM and disk ~1000×+

Speednormal

A modern CPU core executes billions of instructions per second — a single clock cycle is under a nanosecond. But main RAM takes ~100 ns to answer, which is ~200+ cycles. If the CPU had to wait on RAM for every access, it would spend almost all its time stalled, twiddling its thumbs. Caches exist to close this gap.

Access latency

L1 hit~4 cycles

L2 hit~12 cycles

L3 hit~40 cycles

RAM (miss)~200 cycles

Cache line64 bytes

Loop orderhits vs misses

Active Recall

Question 1 / 3

When the CPU reads one uncached byte, how much does the hardware actually fetch?

Under the Hood

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DNSresolving host

TCPconnecting

TLShandshake

HTTPrequesting

DSAverse

CPU Cache Hierarchy

CPU Cache Hierarchy